3GPP Kasumi Accelerators

Overview

The Kasumi-IP-06 (EIP-06) cipher accelerators implement the specification of the 3GPP Confidentiality and Integrity Algorithms as specified in 3GPP TS 35.201 and 3GPP TS 35.202. Designed for fast integration, low gate count and full transforms, the Kasumi-06 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into high speed SoCs for base stations or other equipment requiring 3GPP support.

The Kasumi-IP-06 is a family of the cryptographic library elements in the Rambus hardware IP library (formerly of Inside Secure). For example, the Kasumi-IP-06 is the cipher core embedded in some PacketEngine-IP-97/196/197 protocol-aware security engines. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.

Sustained performance for any object sizes ranges from 2.4 to 5 Gbps depending on the configuration, area and frequency. Gate count is around 20K gates depending on the configuration. Supported modes: UEA2, UIA2, f8. F9.

Key Features

  • Wide bus interface (64-bit data, 128-bit keys) or 32-bit register interface.
  • Includes key scheduling hardware.
  • Modes Kasumi
  • Algorithms f8 and f9.
  • Fully synchronous design.
  • Low Speed, High Speed versions.

Benefits

  • Silicon-proven implementation
  • Fast and easy to integrate into SoCs
  • Flexible layered design.
  • Complete range of configurations
  • World-class technical support

Block Diagram

3GPP Kasumi Accelerators Block Diagram

Technical Specifications

Foundry, Node
Any
Maturity
Silicon Proven
Availability
Now
TSMC
Silicon Proven: 7nm , 16nm , 28nm , 40nm G
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Semiconductor IP