Special IP for TSMC

A mixed Digital and Analog Library, compatible with I2C and I3C Protocols.
This library is a mixed Digital and Analog library built for the TSMC 65nm process.
It is based around a Fail-Safe General Purpose Input/Output (FSGPIO) cell that is compatible with both I2C and I3C protocols.

This 1.8V SLVS transceiver is a high-performance, low-power I/O solution optimized for TSMCs 28nm process.
Designed with 1.8V thick oxide devices and a standard low-voltage core interface at 0.8V, this transceiver ensures robust operation across a wide temperature range (-40°C to 125°C).
Supporting high-speed differential signaling up to 2Gbps, it delivers ex- ceptional signal integrity with low jitter and precise eye diagrams.

A 1.0V to 5V Analog I/O library that includes an HDMI, LVDS, and Analog/RF Low Capacitance pad set in TSMC 45/40nm HPM process.
This library is collection of analog only IO and Power/Ground pads that include ESD. The target applications are high performance analog interfaces including HDMI, RF, LVDS, basic analog and other applications.
The pads include a host of specialty features including fail safe, low capacitance, high ESD protection, and IEC robustness.

A radiation-hardened TSMC 130nm Wirebond I/O Library with 3.3V GPIO, 3.3V LVDS TX & RX, 3.3V I2C ODIO, 3.3V Analog cell, OTP cell, and associated ESD.
Key attributes of this silicon-proven, radiation hardened I/O library include an extended operational temperature range (-50C to 200C), a sleep retention mode, and a built in power regulation PMOS device for core VDD.

A TSMC 130nm Wirebond/Flipchip compatible I/O Library with 5V GPIO, 5V ODIO, 5V Analog I/O and 5V Power Supply I/O.
This silicon-proven, I/O Library features a 5V General Purpose I/O, 5V Open-Drain I/O, 5V Analog I/O, 5V Power Supply and an area efficient 5V ESD protection scheme.

A TSMC 22nm Wirebond / Flipchip I/O library with dynamically switchabe 1.8V/3.3V GPIO, 3.3V I2C ODIO, 3.3V Analog Cell and associated ESD.
This is an ultra-low leakage library. The GPIO has a worst-case leakage of only 425nA.
It works with a wide VDDIO supply range from 1.8V to 3.3V during system operation without the need for the customer to manually switch between high and low-voltage modes.

Wide output frequency range support for diverse clocking needs
Implemented with Analog Bits’ proprietary architecture
Low power consumption
Requires no additional on-chip components or band-gaps, minimizing power consumption

CML differential buffer for on-chip applications
Wide Ranges of input frequencies for diverse clocking and data needs
Implemented with Analog Bits’ proprietary architecture
Requires no additional on-chip components or band-gaps, minimizing power consumption

High speed, source synchronous, bi-directional I/O buffer supporting the Open NAND Flash Interface (ONFI) 3.0 standard
Operation up to 200MHz DDR (400Mbps) performance with single load topology
Designed with core and 1.8V IO oxide devices
Built-in ODT (On-Die Termination)