Ultra-low leakage I/O Library in TSMC 22nm

Overview

A TSMC 22nm Wirebond / Flipchip I/O library with dynamically switchabe 1.8V/3.3V GPIO, 3.3V I2C ODIO, 3.3V Analog Cell and associated ESD.

This is an ultra-low leakage library. The GPIO has a worst-case leakage of only 425nA. It works with a wide VDDIO supply range from 1.8V to 3.3V during system operation without the need for the customer to manually switch between high and low-voltage modes. The GPIO cell set can be configured as input or output and has an internal 50K ohm pull-up or pull-down resistor. It has a sleep function which - when enabled - puts the I/O into an ultra-low power state and latches the I/O in the previous state. Cells for I/O, core power, and ground with built-in ESD circuitry are included. A power-on-control circuit is integrated into an available VDDIO cell. The GPIO can do TX and RX up to 150MHz. ESD targets are 2KV HBM / 500V CDM with 2KV IEC 61000-4-2 system stress capability.

Operating Conditions

Parameter Value
VDDIO 1.8V - 3.3V
Core VDD 0.9V
Temperature -40C to 125C
ESD 2kV HBM & 500V CDM

Cell Size and Metal Stack

Cell Size Metal Stack
65um x 80um 1P7M_4x1Z1U

Cell Summary

Cell Type Feature
Supply/ESD 1.8V - 3.3V; GND
GPIO 150-300MHz (supply dependent

ESD Summary

  • Complies with xSPI266
  • Complies with xSPI333 when VDDIO = 2.5V
  • Complies with xSPI400 when VDDIO = 3.3V

Key Features

  • Typical leakage < 160nA
  • 150MHz low-leakage general purpose I/O (GPIO)
  • Dynamic 1.8V - 3.3V operation
  • 150MHz - 300MHz transmit and receive
  • Full-speed output enable
  • Independent power sequencing
  • Schmitt trigger receiver
  • 50K selectable pull-up or pull-down resistor
  • ESD: 2kV HBM, 500V CDM, 2kV IEC 61000-4-24

Block Diagram

Ultra-low leakage I/O Library in TSMC 22nm Block Diagram

Technical Specifications

TSMC
In Production: 22nm
Pre-Silicon: 22nm
Silicon Proven: 22nm
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