Single-Port SRAM IP for TSMC
Welcome to the ultimate
Single-Port SRAM IP
for
TSMC
hub! Explore our vast directory of
Single-Port SRAM IP
for
TSMC
All offers in
Single-Port SRAM IP
for
TSMC
Filter
Compare
14
Single-Port SRAM IP
for
TSMC
from
5
vendors
(1
-
10)
-
High-Density eMRAM Compiler TSMC 22ULL
- eMRAM compiler enabling low-power designs requiring high memory capacity
-
GCRAM, the highest-density on-chip embedded memory in standard CMOS
- High-density bitcell offering up-to 2X area reduction over high-density 6T SRAM.
- Full logic compatibility with standard CMOS, no additional process steps or cost.
-
Single Port SRAM compiler - Memory optimized for ultra high density and low power - compiler range up to 576 k
- Configuration
- SVT transistors for memory periphery
- HD HVT Pushed rule bit cell from foundry
- Smart periphery design
-
Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k
- Foundry sponsored memory generator
- Configuration
- uLL TSMC Bit-cell for memory core and uLL MOS for memory periphery
- Migration of an existing architecture already available for other processes (90, 85, 55 nm)
-
Single Port SRAM compiler - Memory optimized for ultra high density and high speed - compiler range up to 320 k
- Configuration
- SVT MOS for memory periphery
- uHD HVT pushed rule bit-cell from foundry
- Smart periphery design to reach the highest density
-
Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k
- ConfigurationSVT/HVT MOS for memory peripheryuHD HVT pushed rule bit-cell from foundry Designed with 4 metal layers, routing enabled over the memory in metal 4 within free routing tracksMigration on an existing architecture already available for other processes (90, 85, 55 nm)Smart periphery design to reach the highest densityUp to 20% denser than standard memory generators at 55 nmUltra low leakage designData retention mode at nominal voltage (1.2 V) and low voltage (0.7 V): for 4x leakage reductionLow dynamic powerPartitioned arrayVariable write-mask capability Easy integrationMUX optionsData range flexibility allows easy addition of bits for redundancy or ECC purposesAddress range flexibility allows easy addition of single rows for redundancy purposes The Dolphin qualityComplete mismatch validation of the memory architecture taking in account local and global dispersionOptional BIST for industrial fabrication test of instances
-
Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k
- Migration of an existing architecture already available for other processes (90, 85, 55 nm)
- Smart periphery design to reach the highest density
- Memory designed with SVT MOS for periphery and SVT uHD PRBC from TSMC for memory core
- Ultra Low dynamic power
-
Single Port SRAM compiler - Memory optimized for high density and low power - Deep N Well supported - compiler range up to 320 k
- REACH THE HIGHEST DENSITY
- Thanks to smart periphery design
- Typically up to 20% gain in density versus alternative HD-LP RAM depending on instance configuration
- Using Pushed Rules Foundry bitcell
-
Foundry sponsored - Single Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 320 k
- FOUNDRY SPONSORED
- HIGHEST DENSITY
- -Smart periphery design
- -Typically up to 20% gain in density versus alternative HD-LP RAM depending on instance configuration
-
Single Port SRAM compiler - Memory optimized for ultra low power and high density - Dual Voltage - compiler range up to 512 k
- Reduced die cost
- Pushed rule bit cell from foundry
- Ultra low power
- Low voltage operation down to 1.2 V