Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k
Overview
Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k
Key Features
- ConfigurationSVT/HVT MOS for memory peripheryuHD HVT pushed rule bit-cell from foundry Designed with 4 metal layers, routing enabled over the memory in metal 4 within free routing tracksMigration on an existing architecture already available for other processes (90, 85, 55 nm)Smart periphery design to reach the highest densityUp to 20% denser than standard memory generators at 55 nmUltra low leakage designData retention mode at nominal voltage (1.2 V) and low voltage (0.7 V): for 4x leakage reductionLow dynamic powerPartitioned arrayVariable write-mask capability Easy integrationMUX optionsData range flexibility allows easy addition of bits for redundancy or ECC purposesAddress range flexibility allows easy addition of single rows for redundancy purposes The Dolphin qualityComplete mismatch validation of the memory architecture taking in account local and global dispersionOptional BIST for industrial fabrication test of instances
Technical Specifications
Maturity
In_Production
TSMC
In Production:
55nm
LP
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