PLL IP for TSMC
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All Digital Fractional-N RF Frequency Synthesizer PLL in TSMC N6/N7
- Fractional Multiplication with frequencies up to 8GHz
- Extremely low jitter (sub 300fs RMS)
- Small size (< 0.05 sq mm)
- Low Power (< 7mW)
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Low Power All Digital Fractional-N PLL in TSMC N6/N7
- Low power, suitable for IoT applications
- Good jitter, suitable for clocking digital logic.
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
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Low Power All Digital Fractional-N PLL in Samsung 8LPP
- Low power, suitable for IoT applications
- Good jitter, suitable for clocking digital logic.
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
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Low Power FracN/SSCG PLL on TSMC CLN6FF
- Electrically Programmable PLL with Fractional-N divide and Spread Spectrum Clock Generation
- Wide Ranges of Input and Output Frequency for diverse clocking needs
- Very fine precision: near 1 part per billion resolution
- Fully integrated 32-bit datapath (8-bit integer plus 24-bit fractional)
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4.8GHz low jitter fractional-N, Digital PLL, TSMC N6, 0.75V, N/S orientation
- Pure core voltage design
- Compact IP size (< 0.013mm²) and low power consumption (1.1mW @ 3GHz)
- Compatible with commonly used crystal oscillator frequencies
- Good power noise immunity for period jitter (< ±15%/V)
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Wide Range Programmable Integer PLL on TSMC CLN6FF
- Electrically Programmable PLL for multiple applications
- Wide Ranges of Input and Output Frequency for diverse clocking needs
- Implemented with Analog Bits’ proprietary architecture
- Low power consumption
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Wide Range Multi-Output PLL on TSMC CLN6FF
- Electrically Programmable PLL for multiple applications
- Wide Ranges of Input and Output Frequency (including multiple outputs) for diverse clocking needs
- Implemented with Analog Bits’ proprietary architecture
- Low power consumption
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PCIe Gen4/5/6 Class Low Jitter LC PLL on TSMC CLN6FF
- High performance design emphasis for meeting low jitter requirements in PCIe Gen3/4/5 applications
- Implemented with Analog Bits’ proprietary LC architecture
- Low power consumption
- Spread Spectrum Clock Generation (SSCG) and tracking capability
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High Speed Multi-Phase PLL on TSMC CLN6FF
- Electrically Programmable PLL for multiple applications
- Wide Ranges of Output Frequency for diverse clocking needs
- Implemented with Analog Bits’ proprietary architecture
- Low power consumption
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High Performance 20GHz PLL on TSMC CLN6FF
- Electrically Programmable PLL for multiple applications
- Implemented with Analog Bits’ proprietary architecture
- Low power consumption
- Integrated LDO to reduce deterministic jitter