The PCIe Gen5 Ref Clock SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3, Gen4 and Gen5 serial bus standard where SRIS (Separate RefClk Independent Spread-spectrum clock generation) is required. This SSCG PLL is designed for digital logic processes and use robust design techniques to work in noisy SoC environments.
The PLL macro is implemented in Analog Bits’proprietary architecture that uses core and 1.8V IO devices.
Eliminating band-gaps and integrating all on-chip components such as capacitors helps the jitter performance significantly and reduces stand-by power.
SSCG PLL Operational Range Description Symbol Min Typ Max Units Input Frequency FREF 24 25 38.4 MHz VCO Frequency FVCO 4800 MHz Output Frequency FOUT 100 MHz Output Duty Cycle tDO 48 52 % Lock Time tLOCK 20 µs Reset Time tRESET 1 µs Bypass Mode fBYPASS 100 MHz PLLOUT Random Jitter (see NOTE2, unfiltered) RJPO 1.03 ps-RMS PLLOUT Random Jitter (see NOTE2, filtered) RJPO 0.081 ps-RMS Modulation Frequency FM 30 33 kHz Modulation Depth (down-spread) DMD -0.5 0 % Area A 0.12 sq. mm Total Power IDD 12 20 mW Output Load CL 100 fF Operational Voltage (Digital) VDIG 0.675 0.75 0.825 V Operational Voltage (Analog) VANA 1.62 1.8 1.98 V Operational Temperature TOP -40 25 125 C Table 1: SSCG PLL Operational Range