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DLL IP for TSMC

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Compare 397 DLL IP for TSMC from 4 vendors (1 - 10)
  • 800/1000 MHz DLL-based frequency multiplier
    • TSMC 90 nm CMOS
    • Low jitter
    • Precisely aligns the clock distribution output with a reference clock
    • Low current consumption
    Block Diagram -- 800/1000 MHz DLL-based frequency multiplier
  • 30-200 MHz DLL-based frequency multiplier
    • TSMC CMOS 55 nm
    • 30 – 200 MHz output frequency
    • 7.5 – 100 MHz reference frequency
    • Multiplication factor 1, 2, 3 or 4
    • Glitch-free mode switching
    Block Diagram -- 30-200 MHz DLL-based frequency multiplier
  • 800Mb/s DDR DLL on TSMC CLN55LP
    • Generates precise degrees of clock phase shifting for mobile or standard DDR applications
    • Phase adjustments of non-continuous strobe clocks
    • Compensates for external clock and data delays
    • Programmable delay for precise and granular control of delay
  • TSMC CLN90LP 90nm Multi Phase DLL - 120MHz-600MHz
    • Designed for high-speed interface applications.
    • Generates precise multi-phase clocks directly from the reference clock.
    • Delivers optimal jitter performance over a wide frequency range.
  • TSMC CLN90LP 90nm Multi Phase DLL - 60MHz-300MHz
    • Designed for high-speed interface applications.
    • Generates precise multi-phase clocks directly from the reference clock.
    • Delivers optimal jitter performance over a wide frequency range.
  • TSMC CLN90LP 90nm Multi Phase DLL - 240MHz-1200MHz
    • Designed for high-speed interface applications.
    • Generates precise multi-phase clocks directly from the reference clock.
    • Delivers optimal jitter performance over a wide frequency range.
  • TSMC CLN90LP 90nm DDR DLL - 164MHz-820MHz
    • Designed for high-speed DDR style interface applications.
    • Generates precise delays that can be programmed from 0 to 360 degrees of the reference period.
    • Delays multiple periodic or aperiodic signals independent of voltage and temperature.
    • Delivers optimal jitter performance over a wide frequency range.
  • TSMC CLN90LP 90nm DDR DLL - 78MHz-390MHz
    • Designed for high-speed DDR style interface applications.
    • Generates precise delays that can be programmed from 0 to 360 degrees of the reference period.
    • Delays multiple periodic or aperiodic signals independent of voltage and temperature.
    • Delivers optimal jitter performance over a wide frequency range.
  • TSMC CLN90LP 90nm DDR DLL - 104MHz-520MHz
    • Designed for high-speed DDR style interface applications.
    • Generates precise delays that can be programmed from 0 to 360 degrees of the reference period.
    • Delays multiple periodic or aperiodic signals independent of voltage and temperature.
    • Delivers optimal jitter performance over a wide frequency range.
  • TSMC CLN90GT 90nm Multi Phase DLL - 250MHz-1250MHz
    • Designed for high-speed interface applications.
    • Generates precise multi-phase clocks directly from the reference clock.
    • Delivers optimal jitter performance over a wide frequency range.
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