Memory Interfaces IP for SMIC

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Compare 4 Memory Interfaces IP for SMIC from 2 vendors (1 - 4)
  • DDR4 IO for memory PHY, 3200Mbps on SMIC 40nm
    • The DDR4 IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM device
    • The TX is designed to send information from PHY to DRAM and RX is designed to receive information which is from DRAM.
  • 7 way DDR combo
    • Full DDR4 capability
    • Full DDR3 / DDR3L / DDR3U capability
    • Full LPDDR4 capability
    • Full LPDDR3 capability
  • SSTL_15 IO Pad Set
    • ? Full DDR3 capability - 800MHz (1600 MT/s)
    • ? Low Power driving standard DDR3 memories
    • ? User programmable ODT Capability - dynamic 6-Bit PVT calibration to an external reference resistor
  • SSTL_15 / SSTL_18 Combo I/O Pad Set
    • ? Full DDR3 capability - 800MHz (1600 MT/s)
    • ? Full DDR2 capability
    • ? Low Power driving standard DDR3 memories
    • ? User programmable ODT Capability - dynamic 6-Bit PVT calibration to an external reference resistor
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Semiconductor IP