The SSTL_15 pad set supports bidirectional single-ended and
differential SSTL_15 signaling. The driver/receiver pairs, with
embedded power cells, are supplied with a full complement of
calibration, voltage reference, power, spacer, and adapter cells to
assemble a pad ring by abutment. An included rail splitter allows
isolated SSTL_15 domains (1.5V) to be placed in the same pad ring
with 2.5V/3.3V GPIO domains while maintaining continuous
VDD/VSS in the pad ring for robust ESD protection.
SSTL_15 IO Pad Set
Overview
Key Features
- ? Full DDR3 capability - 800MHz (1600 MT/s)
- ? Low Power driving standard DDR3 memories
- ? User programmable ODT Capability - dynamic 6-Bit PVT calibration to an external reference resistor
Deliverables
- a. Physical abstract in LEF format (.lef)
- b. Timing models in Synopsys Liberty formats (.lib and .db)
- c. Calibre compatible LVS netlist in CDL format (.cdl)
- d. GDSII stream (.gds)
- e. Behavioral Verilog (.v)
- f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- g. Databook (.pdf)
- h. Library User Guide - ESD Guidelines (.pdf)
Technical Specifications
Foundry, Node
SMIC 40nm
Maturity
Silicon Proven
Availability
Available Now
SMIC
Silicon Proven:
40nm
LL