7 way DDR combo

Overview

The LPDDR2/3_DDR3/4 libraries contain the 7-way combo driver/receiver cells with embedded power cells, the driver impedance calibration cell, and the DDR voltage reference cell providing both single-ended and differential signaling for LPDDR2, LPDDR3, LPDDR4, DDR3, DDR3L, DDR3U, and DDR4 applications. Also included is a full complement of power, corner and spacer cells to assemble a complete pad ring by abutment. An included rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.

Key Features

  • Full DDR4 capability
    • Data rates – 1600 MT/s, 1866 MT/s, 2133 MT/s, 2400 MT/s
  • Full DDR3 / DDR3L / DDR3U capability
    • Data rates – 800 MT/s, 1066 MT/s, 1333 MT/s, 1600 MT/s, 1866 MT/s, 2133 MT/s
  • Full LPDDR4 capability
    • Data rates – 1066 MT/sec, 2400 MT/sec, 3200 MT/sec, 4266 MT/sec
  • Full LPDDR3 capability
    • Data rates – 1333 MT/sec, 1600 MT/sec
  • Full LPDDR2 capability
    • Data rates – 466 MT/sec, 1066 MT/sec
  • User programmable drive strength
    • DDR3 – ZOUT = 34 / 40 ?
    • DDR4 – ZOUT = 34 / 48 ?
    • LPDDR2 – ZOUT = 34 / 40 / 48 / 60 / 80 ?
    • LPDDR3 – ZOUT = 34 / 40 ?
    • LPDDR4 – ZOUT = 40 / 48 / 60 / 80 / 120 / 240 ?
  • User programmable on-die termination
    • DDR3 – 120 / 60 / 40 / 30 / 24 / 20 / 17 ?
    • DDR4 – 240 / 120 / 80 / 60 / 48 / 40 / 34 ?
    • LPDDR3 – 240 / 120 / 80 / 60 / 48 / 40 / 34 ?
    • LPDDR4 – 240 / 120 / 80 / 60 / 48 / 40 / 34 ?

Deliverables

  • Final deliverables for the Licensed Product do not include test chip,
  • silicon verification and characterization results, but shall include:
  • a. Physical abstract in LEF format (.lef)
  • b. Timing models in Synopsys Liberty formats (.lib and .db)
  • c. Calibre compatible LVS netlist in CDL format (.cdl)
  • d. GDSII stream (.gds)
  • e. Behavioral Verilog (.v)
  • f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
  • g. Databook (.pdf)
  • h. Library User Guide - ESD Guidelines (.pdf)

Technical Specifications

Foundry, Node
TSMC 16nm
Maturity
Silicon Proven
Availability
Available Now
GLOBALFOUNDRIES
In Production: 28nm SLP , 55nm , 55nm LPX , 65nm LPe , 130nm , 130nm HP , 180nm LL
Silicon Proven: 28nm HPP , 28nm SLP , 40nm LP , 55nm LPX , 65nm LPe , 90nm LP
SMIC
Silicon Proven: 40nm LL
TSMC
Silicon Proven: 16nm
UMC
Silicon Proven: 55nm
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Semiconductor IP