Analog IP for SMIC
Welcome to the ultimate Analog IP for SMIC hub! Explore our vast directory of Analog IP for SMIC
All offers in
Analog IP
for SMIC
Filter
Compare
409
Analog IP
for SMIC
from 22 vendors
(1
-
10)
-
Fractional-N Frequency Synthesizer PLL
- Wide functional range allows all frequencies in a system to be synthesized with one PLL macro
- Input & output frequency ranges greater than 1000:1
-
High Performance Fractional-N RF Frequency Synthesizer PLLs for 5G, WiFi, etc
- Fractional-N digital PLL architecture, using an LC-tank oscillator
-
Low Voltage, Low Power Fractional-N PLLs
- Low power, suitable for IoT applications
- Good jitter, suitable for clocking digital logic.
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
-
General Purpose Fractional-N PLLs
- Low power, suitable for logic clocking applications
- Extremely small die area, using a ring oscillator
- Twelve bits fractional resolution
-
Fractional-N PLLs for Performance Computing
- Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 4GHz
- Reference clock from 10MHz to 500MHz
-
24-bit Cap-less ADC 106 dB SNR
- I2C and APB control interface
- Embedded low noise voltage regulator for best resilience to power supply noise
- Low BoM and capacitor-less input connection
- High dynamic range for high quality recording in far-field applications
-
24-bit Cap-less ADC 106 dB SNR low power and low latency 3 channels
- I2C and APB control interface
- Embedded low noise voltage regulator for best resilience to power supply noise
- Low BoM and capacitor-less input connection
- High dynamic range for high quality recording in far-field applications
-
Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks
- Low noise: high power Supply Rejection Ratio (PSRR): - 65 dB at F < 10 kHz
- Low intrinsic noise: 20 uVRMS at 10 Hz to 20 kHz
- Low Bill-of-Material: optimized in density for the best trade-off for the given output current and input voltage range
- Cost efficient solution compared to external Power Management.
-
PVT Sensor Subsystem
- Start-up time: Typ 20us
- Current consumption: Max 25uA
- Industry standard digital interface
-
Sleep Management Subsystem
- Power-On-Reset
- Programmable relaxation oscillator
- Low Power Comparator
