I/O Library IP for Silterra

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Compare 14 I/O Library IP for Silterra from 3 vendors (1 - 10)

1.25 Gbps 4-Channel LVDS Deserializer in Samsung 28FDSOI
- 25-180 MHz clock support
- Up to 1.25 Gbps bandwidth
- Up to 5.0 Gbps data throughput
- Full Low power CMOS design
1.25 Gbps Four-Channel (4CH) LVDS Serializer with Pre-emphasis
- 25-180 MHz clock support
- Up to 1.25 Gbps bandwidth
- Up to 5.0 Gbps data throughput
- Low power CMOS design
High voltage tolerant I/O
- Scalable robustness
- Area efficient
- low capacitance option
Analog I/O - low capacitance, low leakage
- Scalable robustness
- Area efficient
- low capacitance option
on-chip ESD protection
- Analog I/Os
- ESD Power protection
- Ground pads
- ESD protection cells
On-chip protection against IEC61000-4-2 events
- Analog Pads
- Power Pads
- Ground Pads
Dual FPD-link, 30-Bits Color LVDS Receiver, 170Mhz (SVGA/FHD@120Hz) LVDS de-serializer 10:70 channel decompression with automatic de-skew
- Layout structure based on 0.13um Logic 1P6M, 1P7M, or 1P8M Salicide 1.2V/3.3V process.
- 1.2V/3.3V ±10% supply voltage, -40/+125°C
- Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3- 1996+ ANSI/TIA/EIA-644-A Specifications.
- Up to 11.9Gbps bandwidth (40 to 170Mhz pixel clock) per pixel channel (Full HD @ 120Hz)
Dual RSDS Transmitter, 30-bit color, 40-300Mb/s (SVGA/UXGA/full HDTV) LCD & Plasma display
- • 20 to 150 Mhz Pixel rate per channel ( 40 to 300 Mb/s SDR input, 40 to 300 Mb/s DDR output )
- • 30 DATA + 9 RSDS CLK channels
- • Complies with RSDS “Intra-Panel” Interface Specification rev1.0, May 2003.
- • 1P6M layout structure based on 0.18um 1P6M generic logic process.
Dual FPD-link Transmitter, 24 Bits Color, 20-170 Mhz (SVGA/UXGAW/Full HDTV)
- • 1P6M layout structure based on 0.13um 1P6M 1.8V/3.3V generic logic process.
- • 3.3V/1.8V ±10% supply voltage, 0/+125°C
- • Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard
- 1596.3-1996+ ANSI/TIA/EIA-644-A Specifications.
FPD-link, 30Bits Color LVDS Receiver, 150Mhz (SVGA/WXGA)
- 1P6M layout structure based on 0.18um 1P6M 1.8V generic logic process.
- 3.3V/1.8V 10% supply voltage, 0/+125C
- Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3-1996+ ANSI/TIA/EIA-644-A Specifications.
- Up to 3.15Gbps bandwidth (8 to 90Mhz pixel clock for 1 channel)