Dual FPD-link Transmitter, 24 Bits Color, 20-170 Mhz (SVGA/UXGAW/Full HDTV)

Overview

Now available up to 170 Mhz per channel !

This FPD Link Transmitter Macro is based on National emiconductor openLDI specification v0.95 dated May 13th 1999 that allow the transfer of digital display data between a display source and a display device.
This transmitter converts 8 LVDS, (low voltage differential ignaling) data streams, into up to 48 bits (dual pixel 24-bits) CMOS data plus 8 control signals (VSYNC, HSYNC, DE, and 5 user defined signals).
At a maximum pixel rate of 170Mhz, LVDS data line speed is 1190Mbps, providing a total maximum bandwidth of 9.52Gb/s (1190Mbytes per second).

Key Features

• 1P6M layout structure based on 0.13um 1P6M 1.8V/3.3V generic logic process.
• 3.3V/1.8V ±10% supply voltage, 0/+125°C
• Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard
1596.3-1996+ ANSI/TIA/EIA-644-A Specifications.
• Up to 7.56Gbps bandwidth (20 to 135Mhz pixel clock)
• support Full HDTV
• Spread-spectrum input clock support (can be used in SS systems)
• Output Swing Control (2.5mA to 7mA), PVT compensated
• Core cell area: [contact us]
• Built-in power pads with ESD protection.
• Low leakage power-down mode <10uA.
• Equivalent part : Thine’s THC63LVD823

Deliverables

Design kit includes :
- LEF view and abstract gdsII
- Verilog HDL behavioral model
- Liberty (.lib) timing constraints for typical, worse and best corner case
- Full Datasheet /Application Note with integration guidelines document
- Silicon characterization report when available

Technical Specifications

Maturity

pre-silicon

Availability

now

SMIC

Pre-Silicon: 180nm G

Silterra

Pre-Silicon: 180nm

TSMC