Peripheral IP for GLOBALFOUNDRIES

Compare 6 Peripheral IP for GLOBALFOUNDRIES from 5 vendors (1 - 6)

LVDS Deserializer IP
- The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology.
- Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components.
PCIe 3.1 Controller with AXI
- Compliant with the PCI Express 3.1/3.0, and PIPE (16- and 32-bit) specifications
- Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
- Supports Endpoint, Root-Port, Dual-mode configurations
- Supports x16, x8, x4, x2, x1 at 8 GT/s, 5 GT/s, 2.5 GT/s speeds
- Supports AER, ECRC, ECC, MSI, MSI-X, Multi-function, P2P, crosslink, and other optional features
- Supports many ECNs including LTR, L1 PM substates, etc.
Slave side SPI/QPI controller 133MHZ
- SPI
- QPI (Quad I/O SPI)
- 133MHz
Low noise from 8GHz to 11.3GHz differential LC VCO
- Phase noise -108dB typical
- Single 1.2V Power Supply
- VCO center frequencies 8.5GHz, 10.0GHz, 10.7GHz, 11.1GHz
- Each VCO frequency tuning ±8%
Dual RSDS Transmitter, 24/18-bit color, 40-300Mb/s (SVGA/UXGA/full HDTV) LCD & Plasma display
- • 20 to 150Mhz Pixel rate ( 40 to 300 Mb/s SDR input, 40 to 300 Mb/s DDR output)
- • Complies with RSDS “Intra-Panel” Interface Specification rev1.0, May 2003.
- • 1P6M layout structure based on 0.18um 1P6M generic logic process.
- • 3.3V/1.8V 10% supply voltage, -40/+125C
LVDS Transmitter 1250Mb/s, 800Mhz clock with RSDS support
- • 1P6M layout structure based on 0.18um 1P6M 1.8V
- generic logic process.
- • 3.3V/1.8V ±10% supply voltage, -40/+125°C temperature.
- • IEEE Standard 1596.3-1996 and ANSI/TIA/EIA- 644-A Specifications.