The LDPC Error Correction Core (Alcyone) delivers industry-leading error correction performance to enable 2D/3D, SLC/MLC/TLC/QLC NAND Flash for mobile, client and enterprise SSD controller markets. With YEESTOR's patented low-complexity LDPC architecture, Alcyone solves the area and power consumption problems LDPC designs usually have and enables low-power and cost effective SSD controllers. Alcyone has been production proven for different applications such as USB, eMMC and client/enterprise SSD applications. Alcyone is delivered with a complete development package for the ease of use in both FPGA and SoC design.
LDPC Encoder / Decoder
Overview
Key Features
- Support 1KB+/2KB+/4KB+ codeword size
- Support configurable throughput
- Support hard-bit decode (HBD) and soft-bit decode (SBD)
- LDPC hard decoding and soft decoding can be less than 10^-17 UBER at 4K code length
- Built-in low power engine
- Support up to 6bit SBD
- Support variable code rate for various 2D/3D, SLC/MLC/TLC/QLC NAND Flash
- Support byte-by-byte adjustment in user data and parity data area of code word
- Support on-the-fly dynamic code rate swapping
- Support on-the-fly bit error rate monitoring
- Support out-of-order decoding
- Support configurable termination condition
- Qualified on the vendor development platform for both real NAND Flash and AWGN channel model
Benefits
- Very high throughput and error correction capability with low area and power consumption
Block Diagram
Applications
- industrial/enterprise PCIe SSD, USB, and EMMC
Deliverables
- RTL code
- Sanity check RTL simulation environment
- Synthesis script for ASIC and FPGA
- LDPC encoding/decoding C library
- LDPC encoding/decoding matrices
- NAND Flash LLR LUT calibration utility
- Documentations
- Training Course
Technical Specifications
Maturity
In Production, silicon-proven
Availability
available