Forward Error Correction IP

The patented polar encoding and decoding IP for the 3GPP New Radio uplink and downlink includes the entire processing chain, to provide quick and easy integration and minimize the amount of extra work needed.
The polar core uses PC- and CRC-aided SCL polar decoding techniques, in order to achieve compromise-free error correction performance.

The CMS0077 Satellite FEC Decoder has been designed specifically to meet the requirements of the DVB-S2 and DVB-S2X advanced wide-band digital satellite standards.
The core provides all the necessary processing steps to convert a demodulated complex I/Q signal into a standard TS output stream.

Forward-error correction (FEC) channel codes commonly improve the energy efﬁciency of wireless communication systems
Turbo codes are suitable for 3G and 4G mobile communications and satellite communications
You can use Turbo codes in other applications that require reliable information transfer over bandwidth- or latency-constrained communication links in the presence of data-corrupting noise. The 4G Turbo-V Intel® FPGA IP comprises a downlink and uplink accelerator for vRAN and includes the Turbo Intel® FPGA IP.

The 5G Polar Intel® FPGA IP implements a forward error correction (FEC) encoder and decoder based on polar codes compliant with the 3rd Generation Partnership Project (3GPP) 5G specification for integration into your wireless design
Polar codes represent an emerging class of error correction supporting the high throughput requirements for 5G new radio (NR).

Compliant with "Optical Communications Terminal (OCT) Standard Version 3.0, Document ID: SDA-9100-0001-05, August 2021"
Support for payload code rates 11/13, 22/29, 2/3, 1/2, and uncoded data

The DVB-GSE encapsulator and decapsulator IP cores close the gap between network protocols like Ethernet and the physical layer of the DVB family of standards.
The DVB-GSE encapsulator performs the encapsulation of the network layer packets, also referred to as Protocol Data Units (PDUs), into one or more GSE packets, adding control information and performing integrity checks when necessary.

VESA DisplayPort 1.4 compliant
Reed-Solomon RS (254,250) FEC, 10-bit symbols
Two-way interleaving for 1-, 2- and 4-lane modes (4-lane mode requires 2 FEC IP core instances)
DisplayPort main 8b/10b encoder included (Tx only)
Status and control can be done with signals or optionally via an integrated APB register module (Rx)

Compliant with CPRI Specification V7.0, IEEE Standard 802.3.2018 Ethernet specification and JESD204D Specification.
Supports full FEC functionality.
Supports Reed Solomon (544,514) FEC, 10-bit symbols.
Supports different input and output data widths of multiples of 10-bits.

Compliant with CPRI Specification V7.0, IEEE Standard 802.3.2018 Ethernet specification and JESD204D Specification.
Supports full FEC functionality.
Supports Reed Solomon (528,514) FEC, 10-bit symbols.
Supports different input and output data widths of multiples of 10-bits.

HDMI specification 2.1/2.1a and Scalabale Low Voltage Signaling with Embedded Clock (SLVS_EC) compliant.
Supports full FEC functionality.
Supports Reed Solomon (255,251) FEC, 8-bit symbols.
Supports the input and output data widths of multiples of 8-bit.