Our patented polar encoding and decoding IP for the 3GPP New Radio uplink and downlink includes the entire processing chain, to provide quick and easy integration and minimize the amount of extra work needed. The polar core uses PC- and CRC-aided SCL polar decoding techniques, in order to achieve compromise-free error correction performance. Our decoding IP has several parameters, which can be adjusted at synthesis-time to scale the parallelism, latency and throughput. The decoder list size can be reduced from the typical list 8, in order to best fit the required application.
Polar Encoder / Decoder for 3GPP 5G NR
Overview
Key Features
- Fully compliant with the 3GPP NR standard for PUCCH, PUSCH, PDCCH and PBCH. Supports the full range of uncoded and encoded block sizes
- Implements the entire Polar encoding and decoding chain in 3GPP TS38.212
- High error correction performance from Polar PC/CRC-aided decoder core
- Tightly integrates the components in the chain to reduce area usage and latency
- Simple interface, quick to integrate.only the number of uncoded bits (A) and encoded bits (E) needs to be input alongside the bits or LLRs
- FPGA support for Xilinx, Intel and Achronix
- Optimized for ASIC process
- Optimized software solution on Intel Architecture and AVX512 acceleration
- Matlab and C Models available
- Configurable parameters for power and performance optimization
- Scalable design with configurable list size
- Standard AXI interfaces
Benefits
- Encoder
- CRC aided SCL encoding
- Zero padding
- CRC24C attachment
- CRC scrambling and interleaving
- Frozen bit insertion
- Sub block interleaving
- Rate matching
- Decoder
- CRC aided SCL decoding
- Sub block de-interleaving
- Filler bits insertion/removal
- Rate dematching
- Channel de-interleaver
Block Diagram
Applications
- 5G gNodeB
- 5G handset
- 5G test and measurement
Deliverables
- RTL
- C/Matlab Models
- Test bench
Technical Specifications
Availability
Now