Versatile DSP accelerator IP core

Overview

Key Features

• Versatile DSP accelerator IP core,
• Excellent combination of small silicon footprint, computational power and low energy consumption,
• Advanced loop control mechanisms to reduce code size and increase energy efficiency by switching off idle components during loop execution,
• Use of tightly coupled data memory further contributes to low energy consumption and high processing efficiency,
• Predictable and deterministic behavior,
• Efficient hardware and control,
• Exceptionally scalable IP building block,
• Comes with C-based Software Development Environment: Xentium Studio SDE with Eclipse IDE plug-in.
• Fixed-point architecture supporting floating point emulation,
• Versatile: building block for multi-core SoC as well as DSP accelerator core for general purpose processor,
• Small silicon footprint,
• High instruction-level parallelism with 10 execution slots,
• 32/40-bit scalar and two 16-bit element vector operations,
• Easy integration in NoC-based or bus-based SoC,
• Energy efficient due to advanced control logic and loop techniques,
• Typical power consumption 0.15 mW/MHz for FFT (90 nm CMOS),
• Customizable RTL soft core with configurable memory sizes and instruction-set customization to optimize for a specific application.

Benefits

• High performance VLIW DSP core,
• High computational performance at low power and small silicon footprint.

Block Diagram

Applications

• Mobile and portable receivers for wireless broadcasting;
• Base stations and mobile devices for wireless communication;
• Multimedia processing;
• Medical imaging;
• Digital beamforming for space applications, radar systems, radio telescopes, and wireless communications;
• Base stations for tracking and tracing RFID.

Deliverables

• synthesizable RTL soft core
• test bench
• SDE (additional)
• software libraries

Technical Specifications