Xccela PSRAM Memory Model

Overview

Xccela PSRAM Memory Model provides an smart way to verify the Xccela PSRAM component of a SOC or a ASIC. The SmartDV's Xccela PSRAM memory model is fully compliant with standard Xccela PSRAM Specification and provides the following features. Better than Denali Memory Models.

Xccela PSRAM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Xccela PSRAM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports Xccela PSRAM memory devices from all leading vendors
Supports 100% of Xccela PSRAM protocol standard
Supports all the Xccela PSRAM commands as per the specs
Supports below Low Power Features

Partial Array Self-Refresh (PASR)
Auto Temperature Compensated Self-Refresh (ATCSR) by built-in temperature sensor
User configurable refresh rate
Ultra Low Power (ULP) Half Sleep mode with data retained

Supports Software Reset
Reset Pin Available
Supports Data Mask (DM) for write data
Supports Data Strobe (DQS) enabled high speed read operation
Supports Register Configurable write and read initial latencies
Supports Write Burst Length, maximum 1024 bytes, minimum 2 bytes
Supports Wrap & Hybrid Burst in 16/32/64/1K lengths
Supports Linear Burst Command

Row Boundary Crossing (RBX) for Read can be enabled via Mode Register
RBX Write is NOT supported
RA[13] Boundary Crossing is NOT supported between 2 dies

Supports 16MB, 32MB, 64MB, 128MB, 256MB density
Supports x16, x8, x1/x4 IO configuration
Checks for following

Check-points include power on, Initialization and power off rules
State based rules, Active Command rules
Read/Write Commands rules etc
All timing violations

Bus-accurate timing for min, max and typical values
Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations
Constantly monitors Xccela PSRAM behavior during simulation
Protocol checker fully compliant with Xccela PSRAM JEDEC draft Specification
Models, detects and notifies the test bench of significant events such as transactions, warnings, timings and protocol violations
Built in functional coverage analysis
Supports callbacks, so that user can access the data observed by monitor

Benefits

Faster testbench development and more complete verification of Xccela PSRAM designs.
Easy to use command interface simplifies monitor control and configuration.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the Xccela PSRAM testcases.
Complete UVM/OVM sequence library for Xccela PSRAM controller.
Examples showing how to connect and usage of Model.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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