Xccela Flash Memory Model

Overview

Xccela Flash Memory Model provides an smart way to verify the Xccela Flash component of a SOC or a ASIC. The SmartDV's Xccela Flash memory model is fully compliant with standard Xccela Flash Specification and provides the following features. Better than Denali Memory Models.

Xccela Flash Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Xccela Flash Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports Xccela Flash memory devices like MT35X_QLJW_U_256_ABA/ MT35X_QLKA_L_01G_BBA/ MT35X_QLKA_U_02G_CBA from all leading vendors
Supports 100% of Xccela Flash protocol Standards.
Supports all the Xccela Flash commands as per the specs.
Supports Single and double transfer rate (SDR/DDR)
Supports following protocols

Octal DDR protocol
Extended-SPI protocol with octal commands

Supports Execute-in-place (XIP).
Supports volatile and nonvolatile configuration settings.
Supports software reset.
Supports 3-byte and 4-byte addressing modes
Supports 64-byte OTP area outside main memory.

Readable and user-lockable
Permanent lock with Program OTP commands

Supports Program/Erase/Suspend operation.
Supports the following Erase capability

Bulk erase
Sector erase 128KB uniform granularity
Subsector erase 4KB, 32KB granularity

Supports security and write protection

Volatile and nonvolatile locking and software write protection
Nonvolatile configuration locking
Password protection
Hardware write protection
CRC

Supports all types of timing and protocol violation detection.
Constantly monitors Xccela Flash behavior during simulation.
Protocol checker fully compliant with Xccela Flash Specification.
Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
Built in functional coverage analysis.
Supports Callbacks, so that user can access the data observed by monitor.

Benefits

Faster testbench development and more complete verification of Xccela Flash designs.
Easy to use command interface simplifies monitor control and configuration.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the Xccela Flash testcases.
Examples showing how to connect and usage of Model.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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