Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs
This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs.
Vendor:
SmartDV Technologies
Category:
SRAM
PSRAM Memory Model
PSRAM Memory Model provides an smart way to verify the PSRAM component of a SOC or a ASIC.
Overview
PSRAM Memory Model provides an smart way to verify the PSRAM component of a SOC or a ASIC. The SmartDV's PSRAM memory model is fully compliant with standard PSRAM Specification and provides the following features. Better than Denali Memory Models.
PSRAM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
PSRAM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
Key features
- Supports PSRAM memory devices from all leading vendors
- Supports 100% of PSRAM protocol standard PSRAM Specification
- Supports all the PSRAM commands as per the specs
- Quickly validates the implementation of the PSRAM standard PSRAM Specification
- Supports Asynchronous and page mode interface
- Supports a burst length of 4, 8, or 16 words.
- Supports Mixed mode operation.
- Supports up to 1GB device density.
- Support PROGRAM or ERASE operations.
- Supports Dual voltage rails for optional performance
- Supports Random access time: 55ns and 70ns
- Supports following Page mode read access
- 16-word page size
- Interpage read access: 55ns and 70ns
- Intrapage read access: 15ns and 20ns
- Support following Low power consumption
- Asynchronous READ
- Intrapage READ
- Standby
- Deep power-down (DPD)
- Supports following Low-power features
- Partial-array refresh (PAR)
- DPD mode
- Supports for Synchronous/asynchronous read
- Synchronous burst read mode
- Random access: 70ns
- Asynchronous page mode: 20ns
- Supports for Partial-array self-refresh (PAR)
- Supports for Automatic temperature-compensated self-refresh (TCSR) for power saving
- Separated I/O power(VccQ) & Core power(Vcc)
- Supports Three state outputs
- Supports Byte read/write control by UB#/LB#
- Supports for 8 page mode & DPD
- Supports following Low Power Feature
- Temperature Controlled Refresh
- Partial Array Refresh
- Deep power-down (DPD) mode
- Supports for full-timing as well as behavioral versions in one model.
- Supports for all timing delay ranges in one model: min, typical and max.
- Constantly monitors PSRAM behavior during simulation.
- Protocol checker fully compliant with PSRAM Specification.
- Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
- Built in functional coverage analysis.
- Supports Callbacks, so that user can access the data observed by monitor
Block Diagram
PSRAM Memory Model block diagram
Benefits
- Faster testbench development and more complete verification of PSRAM designs.
- Easy to use command interface simplifies monitor control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
What’s Included?
- Complete regression suite containing all the PSRAM testcases.
- Complete UVM/OVM sequence library for PSRAM controller.
- Examples showing how to connect and usage of Model.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
Specifications
Identity
Part Number
PSRAM Memory Model
Vendor
SmartDV Technologies
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
SmartDV Technologies
HQ:
India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
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Frequently asked questions about SRAM IP cores
What is PSRAM Memory Model?
PSRAM Memory Model is a SRAM IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this SRAM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.