This IP for DDR4, Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400MHz - 1600MHz, output,frequency synthesizable PLL; UMC 40nm LP Logic Process
Overview
This IP for DDR4, Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400MHz - 1600MHz, output,frequency synthesizable PLL; UMC 40nm LP Logic Process
Technical Specifications
Foundry, Node
UMC 40nm
UMC
Pre-Silicon:
40nm
,
40nm
LP
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