PLL (Frequency Synthesizer) IP, Input: 200MHz - 400MHz, Output: 200MHz - 400MHz, 400MHz - 800MHz, 800MHz - 1600MHz, UMC 65nm LP process
Overview
Input 200MHz - 400MHz, output clock_1X 200MHz - 400MHz, output clock_2X 400MHz - 800MHz, output clock_4X 800MHz-1600MHz, frequency synthesizable PLL, UMC 65nm LP/RVT Low-K Logic process.
Technical Specifications
Foundry, Node
UMC 65nm LP
UMC
Pre-Silicon:
65nm
LP
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