Single-port 16/32/64-bit DDR266 Controller

Overview

The Single-port 16/32/64 bit DDR266 controller IP core is a DDR266 SDRAM controller AMBA AHB back-end. The controller can interface two 16-, 32- or 64-bit DDR266 memory banks to a 32-bit AHB bus. The controller acts as a slave on the AHB bus where it occupies a configurable amount of address space for DDR SDRAM access. The DDR controller is programmed by writing a configuration register mapped located in AHB I/O address space.

Internally, the core consists of an AHB/DDR controller and a technology specific DDR PHY.

Key Features

  • AMBA AHB interface
  • Low area consumption
  • Compatible with AMBA-2.0

Deliverables

  • VHDL source code
  • Synplify project file
  • VHDL test bench
  • Template design for LEON3 processor
  • FPGA evaluation board (optional)

Technical Specifications

Maturity
Production
Availability
Immediately
×
Semiconductor IP