coolREG memory IPs provide solutions for synchronous single-port, dual-port, and two-port register files requirements. The coolREG IP is based on the production-proven, foundry-provided 6T SRAM (single-port) or 8T SRAM (dualor two-port) cell and offers advanced leakage control features and near-zero setup times. These dense memories let the designer specify the number of bits in each word and select the aspect ratio for each specific register file to meet the application’s need.
Novelics patented circuit technologies minimizes leakage current and active power in both the memory core and the peripheral circuits. In addition, the coolREG has been optimized to meet the performance requirements of very high speed applications such as processor cache.
The coolREG IP has been thoroughly simulated and validated in silicon to ensure the highest level of manufacturability. The MemQuest™ memory compiler has been verified and characterized to ensure the highest quality of deliverables.
Novelics coolREG™ embedded memory IPs are ideal solutions for System-on- Chip (SoC), ASIC, and ASSP applications requiring low-power, high-speed, and high-density configurable register files. Embedded coolREG delivers the best performance and power characteristics for small and fast Register File instances.
Synchronous single-port, dual-port, and two-port register files
Overview
Key Features
- Customer architected through the MemQuest memory compiler and characterization tool
- Reliable, silicon-proven architecture
- Single-port, dual-port, and twoport architectures
- Based on foundry-provided 6T SRAM (single port) or 8T SRAM (dual port and two-port) cell
- Support for single and dual clock domains
- In the two-port register file, the read and write ports are completely independent and can read any location simultaneously
- The dual-port clocked register file provides two read and write ports that share the same memory space. Each port can operate in independent clock domains.
- Reliable operation and performance well beyond normal Process/Voltage/Temperature (PVT) variations
- Support for SVT & HVT Transistors
- User definable word width, depth and aspect ratio
- Memory options to meet power, speed, and area design criteria
- Easily configurable options including subword writeable
- Optimized for high performance and low-power designs
- Design utilizes up to 4 layers of metal
- Flexible routing over macro in metal 5 and above
- Supports power mesh
- Minimal setup time
Technical Specifications
Availability
Now
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