FlexRay Controller

Overview

The FlexRay Controller fully complies with FlexRay Communication System Protocol Specification, Version 2.1, Revision A. It implements the specification-defined Controller Host Interface (CHI) and Protocol Engine (PE) functionality, with clean partitioning between the CHI and PE functional blocks.

The FlexRay Controller supports 4–252 message buffers and features standard interfaces to system logic and memories, so it can be readily optimized to your system requirements and easily integrated into your FPGA or ASIC device.

The host CPU interface is similar to the AMBA 2 APB. Example glue logic to connect to AMBA 2 APB is included with the product. The interface to FlexRay memory, which stores the message buffer header, payload, and status, is AMBA 2 AHB and can be adapted to other system memory interfaces upon request.

Hardware Configuration Parameters

OPTION	RANGE	DEFAULT
Maximum number of message buffers	4-252	32
FlexRay memory (AHB) data bus width	32 or 64 (bits)	32

Gate Count and Performance

NUMBER OF MESSAGE BUFFERS	GATES	MIN. CHI FREQUENCY
4	76,720	20
32	83,431	22
252	140,997	135

Key Features

Modular design
- PE cleanly separated from CHI
- Memories external to core
Data transfer is done through message buffers that hold the payload, header, and status information
Single 10-Mbit/s channel for affordability, dual independent channels for 20-Mbit/s, or redundant 10-Mbit/s channels for reliability
Support for lower data rates (2.5, 5 and 8 Mbit/s)
Maskable interrupt signals
Reports on clock synchronization
AMBA interface to host CPU and system memory
Low power consumption through extensive clock gating (optional, may be implemented external to the IP block)
CHI clock independent of PE clock through Clock Domain Crossing
• Configurable:
- Maximum number of message buffers hardware
- configuration option (4-252)
- Message buffer setup programmable at runtime
- Two independent receive FIFOs, each with up to 255 entries and flexible filtering
- Four configurable slot error counters

Block Diagram

Deliverables

Verilog RTL source code
Test bench with test suites
Documentation including User’s Guide and Integration Guide
Technology-independent synthesis constraints

Technical Specifications

Maturity

Silicon Proven

Availability

now

Request Info