FlexRay Controller

Overview

The FlexRay Controller fully complies with FlexRay Communication System Protocol Specification, Version 2.1, Revision A. It implements the specification-defined Controller Host Interface (CHI) and Protocol Engine (PE) functionality, with clean partitioning between the CHI and PE functional blocks.

The FlexRay Controller supports 4–252 message buffers and features standard interfaces to system logic and memories, so it can be readily optimized to your system requirements and easily integrated into your FPGA or ASIC device.

The host CPU interface is similar to the AMBA 2 APB. Example glue logic to connect to AMBA 2 APB is included with the product. The interface to FlexRay memory, which stores the message buffer header, payload, and status, is AMBA 2 AHB and can be adapted to other system memory interfaces upon request.

A rich ecosystem, including support from leading FlexRay software providers and a starter kit available for evaluation and prototyping, enables rapid software development.

Key Features

FlexRay Communications System Protocol Specification, Version 2.1, Revision A compliant protocol implementation
FlexRay Communications System Electrical Physical Layer Specification, Version 2.1, Revision A compliant bus driver interface
TUV conformance tested
Proven in Freescale's MFR43xx and MCP55xx devices
Dual or single channel support
Supports multiple FlexRay bus data rates: 10, 8, 5, and 2.5 Mbit/s (software selectable)
Number of message buffers supported is a hardware configuration option (4-252)
Number of message buffers used is a runtime option
Two independent message buffer groups with runtime-configurable payload size (0-254 bytes)
Each message buffer supports individual frame ID, channel ID, and cycle count filtering
Each message buffer can be configured for transmit or receive
Two transmit message buffers can be combined to form a double-buffered transmit message buffer
Transmit message buffers can be configured for state or event triggered transmission
Zero padding for transmit message buffers in static segment-applied when the frame payload length exceeds the size of the message buffer data section
Message buffers can be safely disabled and reconfigured
Message buffer header, status, and payload data stored in FlexRay memory
Two independent receive FIFOs
Four configurable slot error counters
Four dedicated slot status indicators-used to observe slots without using receive message buffers
Clock synchronization data available to host system
Maskable interrupt sources-individual and combined
Two timers: 1 absolute, 1 absolute or relative
Strobe ports for visibility of selected internal signals
Separate clocks for CHI and PE
Extensive clock gating for low power consumption

Block Diagram

Deliverables

Verilog source code
Integration testbench and tests
Documentation
Scripts for simulation and synthesis with support for common EDA tools

Technical Specifications

Maturity

Silicon Proven

Availability

now

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