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Simulation VIP for MIPI DPI

Overview

Incorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP (VIP) for MIPI® DPIsm Protocols provides a complete bus functional model (BFM), and integrated automatic protocol checks. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for DPI helps you reduce time to test, accelerate verification closure, and ensure end-product quality. DPI VIP is part of DSI VIP. Our VIP for DPI runs on all major simulators and supports SystemVerilog verification language along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported specification: MIPI DPI v2.0

Key Features

  • Transmitter and Receiver
    • Drives or monitors all possible frames
  • Physical Layer
    • Supports all color coding (16/18/24 bits and configuration 1, 2, 3)
  • Timing Parameters
    • Supports all frame timing parameters
  • UVM Configuration
    • The user can configure the VIP agent using the UVM config class
  • Dynamic Activation Support
    • The user can set the VIP as active or passive without changing the testbench, and determine, during run time, which instance to instantiate

    Block Diagram

    Simulation VIP for MIPI DPI Block Diagram

    Technical Specifications

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