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Simulation VIP for MIPI DBI

Overview

Incorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP (VIP) for MIPI® DBI-2sm Protocols provides a complete bus functional model (BFM), and integrated automatic protocol checks. DBI VIP is used with DSI VIP. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for DBI helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Our VIP for DBI runs on all major simulators and supports SystemVerilog verification language along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported specification: MIPI DBI v2.0.

Key Features

  • Configuration/Data
    • Supports protocol checks of signal timings
  • Data
    • Supports a variety of callbacks for better control and monitor functions
  • PHY Interfaces
    • Type A configuration (8,9,16 bits of data bus width)
    • Type B configuration (8,9,16 bits of data bus width)
    • Type C option
  • Physical Layer
    • Supports all signals timing per interface configuration
  • Transmitter and Receiver
    • Drives or monitors all commands from the Display Command Set (DCS)

    Block Diagram

    Simulation VIP for MIPI DBI Block Diagram

    Technical Specifications

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