The Cadence® Verification IP (VIP) for eUSB is a complete VIP solution for the Embedded USB2 (eUSB2) Physical Layer Supplement to the USB Revision 2.0 Specification, Revision 1.1. It provides a mature and comprehensive verification IP (VIP) for the eUSB protocol. Incorporating the latest protocol updates, the eUSB2 VIP is not only just a complete bus functional model (BFM) for the DUT operating in eUSB Native Mode but it also provides integrated automatic protocol checks and coverage model.
This VIP for eUSB provides support for any eUSB device in native mode: Host(eDSPn) or Device(eUSPn), in Repeater Mode: Host(eDSPr) or Device(eUSPr), Host Repeater, Peripheral Repeater and Hybrid Repeater. . It supports all eUSB operational speeds: Low, Full, or High. It provides multiple signaling eUSB interfaces: single-ended signaling for low-/full-speed mode and low-voltage differential signaling for high-speed mode to test and monitor all possible configurations of USB devices. The eUSB VIP is designed in such a way that it is easy for you to integrate in testbenches for IP, System-on-chip (SOC) and system level. The eUSB VIP helps you to reduce time to test by accelerate verification closure and ensure end product quality.
The VIP for USB runs on all major simulators and supports all main verification languages such as Verilog, System Verilog and e alongside with industry-standard methodologies for Testbench writing such as Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).
Supported specifications: eUSB2 2.0, eUSB2 1.0 and USB 1.1.