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MIPI DSI IP

As part of the MIPI (Mobile Industry Processor Interface) standard, MIPI DSI IP supports high-definition video and graphics transmission, making it ideal for smartphones, tablets, automotive displays, and wearables. With its ability to deliver high-quality image output while minimizing power consumption, MIPI DSI IP plays a vital role in enhancing the display performance of modern devices.

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Search (45)
Compare 45 MIPI DSI IP from 16 vendors (1 - 10)
  • MIPI DSI-2 Transmitter Controller IP Core
    • The MIPI Display Serial Interface (DSI-2) Transmitter (host processor interface) Controller IP provides a high-speed serial interface between an application processor and display modules using either MIPI C-PHY v1.1 or MIPI D-PHY v1.2 and v2.0.
    Block Diagram -- MIPI DSI-2 Transmitter Controller IP Core
  • MIPI DSI-2 Receiver IP Controller Core
    • The MIPI Display Serial Interface (DSI-2) Receiver (display panel interface) Controller IP provides a high-speed serial interface between an application processor and display modules using either MIPI C-PHY v1.1 or MIPI D-PHY v1.2 and v2.0.
    Block Diagram -- MIPI DSI-2 Receiver IP Controller Core
  • DSI v1.3 Transmit IP Core
    • The DSI Tx Controller IP is designed to provide MIPI DSI 1.3 – compliant high-speed serial connectivity for the host (mobile application processor) using 1 to 4 D-PHYs depending on bandwidth needs.
    Block Diagram -- DSI v1.3 Transmit IP Core
  • DSI Receiver Controller
    • The DSI v1.3 Receiver Controller IP is designed to provide MIPI DSI 1.3 compliant high-speed serial connectivity for device (mobile display modules) with Type 1 to 4 architectures.
    • Serial connectivity to the mobile applications processor’s DSI host is implemented using 1 to 4 D-PHY’s (also available from Arasan), depending on display bandwidth needs.
    Block Diagram -- DSI Receiver Controller
  • MIPI DSI v2.2 Verification IP
    • Compliant to MIPI DSI Specification version 2.2 and MIPI C-PHY Specification version 2.1 with PPI interface.
    • Support all Calibration Format & operations
    • C-PHY supports MFAA and SFAA for DSI TX and RX respectively for Data Lane Module in command mode.
    • C-PHY supports MFAN and SFAN for DSI TX and RX respectively for data Lane Module in video mode.
    Block Diagram -- MIPI DSI v2.2 Verification IP
  • MIPI DSI v1.3.2 Verification IP
    • Compliant to MIPI DSI Specification version 1.3.2 and MIPI D-PHY Specification version 1.2 with PPI interface.
    • Support all Calibration Formats & operations
    • D-PHY supports MFAA and SFAA for DSI TX and RX respectively for Data Lane Module in command mode.
    • D-PHY supports MFAN and SFAN for DSI TX and RX respectively for Data Lane Module in video mode.
    Block Diagram -- MIPI DSI v1.3.2 Verification IP
  • MIPI  DSI2
    • Fully MIPI DSI-2/DSI standard compliant
    •  64 and 32-bit core widths
    •  Host (Tx) and Peripheral (Rx) versions
    •  Supports 1-4, 9.0+ Gbps D-PHY data lanes
    •  Supports 1-4, 6.0+ Gsym/s C-PHY lane (trio)
    Block Diagram -- MIPI  DSI2
  • MIPI DSI DisplayTransmitter IP
    • MIPI DSI Transmitter IP is designed to transmit the data to the host processor
    • The MIPI DSI-2 provides the mobile industry a standard, robust, scalable, low-power, high-speed, cost-effective interface that supports a wide range of imaging solutions for mobile devices
    •  
    Block Diagram -- MIPI DSI DisplayTransmitter IP
  • MIPI DSI-2 Controller Core
    • Fully MIPI DSI-2/DSI standard compliant
    • 64 and 32-bit core widths
    • Host (Tx) and Peripheral (Rx) versions
    • Supports 1-4, 9.0+ Gbps D-PHY data lanes
    • Supports 1-4, 6.0+ Gsym/s C-PHY lane (trio)
    • Supports all data types
    Block Diagram -- MIPI DSI-2 Controller Core
  • Simulation VIP for MIPI DSI-2
    • Receiver and Transmitter Verification
    • Verifies both DSI processor and peripheral
    • Physical Layer
    • Includes the MIPI D-PHYsm/C-PHYsm VIP for physical layer verification
    Block Diagram -- Simulation VIP for MIPI DSI-2
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