The SHA-3 module implements the SHA3-512, SHA3-384, SHA3-256 and SHA3-224 hash algorithms and the SHAKE128 and SHAKE256 extendable-output functions specified in DRAFT FIPS PUB 202, the Permutation-Based Hash Standard. This module contains all of the digital logic necessary to generate the 512-bit (or 384-bit, or 256-bit, or
224-bit) message digest for a message of arbitrary bit length.
SHA-3 (all variants)
Overview
Key Features
- One clock per step algorithm implementation.
- Automatic rate selection.
- Automatic pad insertion.
- Any bit length message, including zero-length, is allowed.
- Direct Message Digest output, with strobe.
Technical Specifications
Related IPs
- All Digital Phase Locked Loop
- Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core
- HMAC Accelerator with SHA-3, SHA-2, SHA-1
- HASH Accelerator with SHA-3, SHA-2, SHA-1
- DLL (All Digital) IP, Input: 200MHz - 533MHz, Output: 200MHz - 533MHz, UMC 65nm LP process
- DLL (All Digital) IP, Input: 333MHz - 800MHz, Output: 333MHz - 800MHz, UMC 40nm LP process