Vendor: SmartDV Technologies Category: HBM

HBM3 Memory Model

HBM3 Memory Model provides an smart way to verify the HBM3 component of a SOC or a ASIC.

Contact Provider Request Datasheet

Overview

HBM3 Memory Model provides an smart way to verify the HBM3 component of a SOC or a ASIC. The SmartDV's HBM3 memory model is fully compliant with standard HBM3 Specification and provides the following features. Better than Denali Memory Models.

HBM3 Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

HBM3 Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Supports HBM3 memory devices from all leading vendors.
  • Supports 100% of HBM3 protocol draft JEDEC specification version 1.1.
  • Supports all the HBM3 commands as per the specs.
  • Supports programmable clock frequency of operation.
  • Support all types of timing and protocol violation detection.
  • Supports burst length 8.
  • Supports programmable READ/WRITE Latency timings.
  • Supports Bank grouping.
  • Supports 16,32 or 48 banks per channel based on device density and channel.
  • Supports 2KB page size per channel.
  • Supports up to 16 channels per stack.
  • Supports semi-independent row and column command interfaces.
  • Supports WDQS-to-CK training.
  • Checks for following
    • Check-points include power on, Initialization and power off rules,
    • State based rules, Active Command rules,
    • Read/Write Commands rules etc.
    • All timing violations.
  • Supports callbacks for user to get command data on bus.
  • Supports all Mode registers programming.
  • Supports DBIac write and read.
  • Supports Pseudo Channel Mode Operation (32 DQ width for Pseudo Channel Mode).
  • Supports 2 Pseudo channels per channel.
  • Supports Self-Refresh Modes.
  • Supports IEEE standard 1500.
  • Supports channel density of 2 GB to 32 GB.
  • Supports 64 DQ width + Optional ECC pin support/channel.
  • Supports write data mask and data strobe features.
  • Supports for power down features.
  • Supports for input clock stop and frequency change.
  • Bus-accurate timing for min, max and typical values.
  • Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Constantly monitors HBM3 behavior during simulation.
  • Protocol checker fully compliant with HBM3 JEDEC draft Specification version 1.1.
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timings and protocol violations.
  • Built in functional coverage analysis.
  • Supports callbacks, so that user can access the data observed by monitor.

Block Diagram

HBM3 Memory Model block diagram

Benefits

  • Faster testbench development and more complete verification of HBM3 designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the HBM3 testcases.
  • Complete UVM/OVM sequence library for HBM3 controller.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
HBM3 Memory Model
Vendor
SmartDV Technologies
Type
Silicon IP

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

Learn more about HBM IP core

Making Strong Error-Correcting Codes Work Effectively for HBM in AI Inference

LLM inference is increasingly memory-bound, and HBM cost per GB now dominates system cost. Today’s HBM stacks include short on-die ECC, which tightens binning, raises price, and locks reliability policy inside the device. This paper asks a simple question: can we tolerate a much higher raw HBM bit error rate (BER) and still keep end-to-end correctness and throughput, without changing the HBM PHY or the fixed 32B transaction size?

High Bandwidth Memory Evolution from First Generation HBM to the Latest HBM4

HBM4 is the latest generation of the High Bandwidth Memory (HBM) that has become analogous to the Artificial Intelligence (AI) boom that is everywhere in today’s world. HBM is also increasingly being used in other applications like Data centers, autonomous driving systems, servers, cloud computing just to mention few domains where bandwidth and performance in a key requirement.

Breaking the HBM Bit Cost Barrier: Domain-Specific ECC for AI Inference Infrastructure

High-Bandwidth Memory (HBM) delivers exceptional bandwidth and energy efficiency for AI workloads, but its high cost per bit, driven in part by stringent on-die reliability requirements, poses a growing barrier to scalable deployment. This work explores a systemlevel approach to cost reduction by eliminating on-die ECC and shifting all fault management to the memory controller.

High Bandwidth Memory (HBM) Model & Verification IP Implementation - Beginner's guide

With ever increasing need for very high operating frequency of graphics (GPU) or general purpose (CPU) processors, the limited memory bandwidth forms a bottleneck to extract maximum performance out of a system. To add to this, low power consumption, form factor of the memory devices also play significant roles in optimal and efficient solutions.

Frequently asked questions about HBM Interface IP

What is HBM3 Memory Model?

HBM3 Memory Model is a HBM IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this HBM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this HBM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP