PCIe 3.0 PHY in Samsung (SF5A

Overview

The multi-channel Synopsys PHY IP for PCI Express® 3.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ demands for higher bandwidth. The PHY provides a cost-effective solution that is designed to meet the needs of today’s high-speed chip-to-chip, board-to-board, and backplane interfaces while being extremely low in power and area.
Using leading-edge design, analysis, simulation, and measurement techniques, Synopsys delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standard’s electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies.
The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor and test for signal integrity without the need for expensive test equipment. This provides on-chip visibility into actual link and channel performance to quickly improve signal integrity. This capability reduces both product development cycles and the need for costly field support.

Key Features

Physical coding sublayer (PCS) block with PIPE interface
Supports PCIe 3.1, 2.1, 1.1 encoding, backchannel initialization
Spread-spectrum clocking (SRIS)
Supports PCIe power management features, including L1 substate; power gating and power island; DFE bypass option and voltage mode Tx with under drive supply options
Multi-channel PHY macro with single clock and control core for higher density
Supports both internal and external reference clock inputs
PIPE bifurcation as well as PHY macro aggregation for x8 and x16 PHY configurations
Superior Rx jitter & cross talk tolerance reduces design constraints for a wider range of board layout designs
Automated Test Equipment (ATE) test vectors for complete at-speed production testing
Each PHY channel contains its own 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit sequencer (PRBS) for internal and external loopbacks
Each channel is fully controllable via the integrated logic core as well as the test access port (TAP)

Benefits

Compliant with PCIe® 3.1, 2.1, 1.1, and PIPE specifications
x1, x2, x4, x8, x16 lane configurations with bifurcation
Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
L1 substate and Separate Reference Clock with Independent Spread (SRIS) support
Power gating and power island
Embedded bit error rate tester (BERT) and internal eye monitor
Build-in Self Test vectors, PRBS generation and checker
IEEE 1149.6 AC JTAG Boundry Scan
Supports -40°C to 125°C junctions
Supports optional wirebond and flip-chip packaging

Applications

Desktops, laptops, workstations and servers
Embedded systems and set-top boxes
Network switches and routers
Enterprise computing and storage networks
Consumer portable devices
Graphics devices
Wireless devices

Deliverables

Verilog models
Liberty timing views (.lib)
LEF abstracts (.lef)
CDL netlist (.cdl)
GDSII
ATPG models
IBIS-AMI models
Documentation

Technical Specifications

Foundry, Node

Samsung SF5A

Maturity

Available on request

Availability

Available

Samsung

Pre-Silicon: 5nm

UMC

Pre-Silicon: 28nm

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