USB 3.1 PHY (10G/5G) in Samsung (14nm, 11nm, 10nm, 8nm, SF5, SF5A, SF4E)

Overview

The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum. The comprehensive USB 3.1 IP offering consists of Host, Device, and Dual-Role Device controllers, PHYs with and without support for the USB Type-C™ connectivity specification and DisplayPort 1.3 support, verification IP, IP Prototyping Kits, and IP software development kits. These elements enable quick development of advanced chip designs incorporating the 10 Gbps SuperSpeed USB standard. The Synopsys USB 3.1 IP is targeted for integration into SoCs for media storage, creation, and playback devices, requiring faster bandwidth between PCs and portable electronic devices. Optimized for low power, the Synopsys USB 3.1 Controller and PHY IP allow designers to maximize power efficiency for extended battery life. The Synopsys USB 3.1 IP enables the fastest SuperSpeed USB data transfer speeds while lowering overall power consumption. As the leading supplier of USB IP, Synopsys provides designers with a high-performance, low-power, and area-efficient IP solution, for cost-effective integration into system-on-chip designs. Synopsys’ expertise in developing and supporting USB enables us to build a low risk, high quality SuperSpeed USB IP solution.

Key Features

Lowest risk: Based on proven USB 3.0 controller shipped in 100s of millions of units
Lowest power: Extend battery life in mobile devices (USB power saving modes, Uniform Power Format, hibernation option with dual power rails)
Configurable data buffering options to optimize performance vs area
Supports all USB speed modes
Host, Device, and Dual Role Device controllers meet the needs for all markets
USB-C 3.1 DisplayPort 1.3 TX Controller includes HDCP 2.2 content protection

Benefits

Supports SuperSpeed USB 3.1 at 10 Gbps, SuperSpeed USB 3.0 at 5 Gbps, and High-speed USB (USB 2.0) Optimized Host, Device, and DualRole Device controller IP designed to achieve lowest power and area for portable electronics
Synopsys USB-C 3.1/DisplayPort 1.3 TX PHYs and controllers offer high-performance throughput for 4K and 8K display
Supports PIPE and UTMI+ PHY interfaces
Architectural features reduce power consumption
Complete Synopsys USB solutions for USB 3.1 consist of controllers, PHYs, verification IP, IP Prototyping Kits, and IP Software Development Kits
SuperSpeed USB IP offering from the #1 provider of USB IP for thirteen years in a row (Gartner 2014)

Applications

Synopsys coreConsultant tool
Verilog RTL source code
ASIC and FPGA synthesis, ATPG, DFT, power scripts
UVM Testbench with native SystemVerilog Verification IP for USB
Comprehensive databook and integration guides
Reference drivers to speed development
USB-C 3.1 DisplayPort 1.3 TX Controller includes HDCP 2.2 firmware and host API library SDK

Deliverables

Synopsys coreConsultant tool
Verilog RTL source code
ASIC and FPGA synthesis, ATPG, DFT, power scripts
UVM Testbench with native SystemVerilog Verification IP for USB
Comprehensive databook and integration guides
Reference drivers to speed development
USB-C 3.1 DisplayPort 1.3 TX Controller includes HDCP 2.2 firmware and host API library SDK

Technical Specifications

Foundry, Node

Samsung 14nm, 11nm, 10nm, 8nm, SF5, SF5A, SF4E - LPP, LPE

Maturity

Available on request

Availability

Available

Samsung

Pre-Silicon: 4nm , 5nm , 8nm , 10nm , 11nm , 14nm

Request Info