MIPI DSI-2 Receiver Controller v2.0

Overview

Key Features

• DSI-2 Controllers Support
• • MIPI specification of Display Serial Interface (DSI) v2
• • MIPI specification of D-PHY
• • MIPI specification of C-PHY
• • MIPI Alliance standard for Display Pixel Interface (DPI) v2
• • MIPI Alliance standard for Display Bus Interface (DBI) v2
• • MIPI Alliance Standard for Display Command Set (DCS) v2
• Support Display Resolution
• • QCIF, QVGA, CIF, VGA, WVGA, XVGA, 1080HD Display Architecture
• • Type1 display architecture in command mode
• • Type4 display architecture in video mode
• Support video mode and command mode in
• • Type2 and Type3 display Architecture
• • Pixel Formats-RGB565, RGB666, LPRGB666, RGB888, 30bit RGB, 36bit RGB, 16bit YCbCr, 12bit YCbCr, 20bit LP-YCbCr, 24bit YCbCr
• Interface Support for
• • PHY data lane, 32bit for D-PHY, up to 2500Mbps at high-speed.
• • 16bit/32bit per lane for C-PHY, up to 3/6Gsps at high-speed
• • 36bit wide DPI data bus
• • 16bit wide DBI data bus

Benefits

• Fully compliant to MIPI standard
• Small footprint
• Code validated with Spyglass
• Functionality ensured with comprehensive verification
• Product quality proven with silicon
• Premier direct support from Arasan IP core designers.

Block Diagram

Deliverables

• • System Verilog RTL Source Code
• • A simplified Test-bench with simulation models to run initial set of tests after release
• • Synthesizable Netlist
• • Synthesis Scripts and exception lists
• • Timing Report
• • Protocol Compliance & Coverage Report
• • Sample Firmware with Drivers
• • User Guide

Technical Specifications