The MIPI DSI-2 controller core is optimized for high performance, low power and small size. The core is fully compliant with the DSI-2 standard and implements all three layers defined therein: Pixel to Byte Packing, Low Level Protocol, and Lane Management.
MIPI DSI-2 Controller Core
Overview
Key Features
- Fully MIPI DSI-2/DSI standard compliant
- 64 and 32-bit core widths
- Host (Tx) and Peripheral (Rx) versions
- Supports 1-4, 9.0+ Gbps D-PHY data lanes
- Supports 1-4, 6.0+ Gsym/s C-PHY lane (trio)
- Supports all data types
- Easy-to-use native interface
- Delivered fully integrated and verified with target MIPI PHY
Block Diagram
Deliverables
- Core (source code)
- Testbench (source code)
- Complete documentation
- Expert technical support
- Maintenance updates
Technical Specifications
Foundry, Node
Any
Availability
Now