The MXL-DPHY-LVDS-DSI-RX-T-110G is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY and compatible with the TIA/EIA-644 LVDS standard.
The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display serial interface applications (DSI).
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control
MIPI D-PHY/LVDS Combo DSI RX (Receiver) in TSMC 110G
Overview
Key Features
- Consists of 1 Clock lane and 4 Data lanes
- Up to 4.0 Gbps data throughput
- Complies with MIPI Standard 1.0 for D-PHY
- Compatible with TIA/EIA-644 LVDS standard
- Supports both high speed and low-power modes
- 80 Mbps to 1 Gbps data rate in MIPI high speed mode
- 140 Mbps to 945 Mbps data rate in LVDS high speed mode
- 10 Mbps data rate in low-power mode
- High Speed De-Serializers included
- Low power CMOS design
- Power down mode
- 1.2V/3.3V dual power supply
Benefits
- Combo PHY for both MIPI D-PHY DSI RX and LVDS
Applications
- Mobile
- Displays
- IoT
- VR/AR/MR
- Consumer electronics
- Automotive
Deliverables
- Specifications
- GDSII
- LVS netlist
- LEF file
- IBIS Model
- Verilog Model
- Timing Model
- Integration Guidelines
- RTL
- Documentation
- One year support
Technical Specifications
Foundry, Node
TSMC, 110nmG
Maturity
Upon Request
Availability
Now
TSMC
Silicon Proven:
110nm
G