MIPI D-PHY DSI RX (Receiver) in TSMC 110G

Overview

The MXL-DPHY-DSI-RX-T-110G is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI slave with maximum of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display serial interface applications (DSI). The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for
High-Speed Data traffic while low power functions are mostly used for control.

Key Features

Consists of 1 Clock lane and 4 Data lanes
Complies with MIPI Standard 1.1 for D-PHY
Supports both high speed and low-power modes
80 Mbps to 1.0/1.5Gbps data rate in high speed mode
10 Mbps data rate in low-power mode
High Speed De-serializer included
Low power dissipation
Low power CMOS design
Power down mode
1.2V power supply

Benefits

Silicon proven in TSMC 110G

Applications

Mobile
Displays
IoT
VR/AR/MR
Consumer electronics
Automotive

Deliverables

Specifications
GDSII
LVS netlist
LEF file
IBIS Model
Verilog Model
Timing Model
Integration Guidelines
RTL
Documentation
One year support

Technical Specifications

Foundry, Node

TSMC, 110nmG

Maturity

Silicon Proven

Availability

Now

TSMC

Silicon Proven: 110nm G

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