VESA DisplayPort 1.4 Forward Error Correction (FEC) Receiver

Overview

The DisplayPort Forward Error Correction (FEC) Receiver IP core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPort 1.4 specification. Forward Error Correction is required to ensure glitch-free Display Stream Compression (DSC) bitstream transport.

Key Features

VESA DisplayPort 1.4 compliant
Reed-Solomon (254,250) FEC, 10-bit symbols
Two-way interleaving for 1-, 2-, and 4-lane modes (4-lane mode requires 2 FEC IP core instances)
Optionally includes the DisplayPort main 8b/10b decoder
Status and control can be done with signals or optionally via an
integrated APB register interface module
Single unified APB interface supports 4-lane mode

Benefits

IP customization and integration services available on request
Multi-project licenses available
UVM verification bindable modules

Block Diagram

Applications

UHD monitors
DisplayPort 1.4 products
USB Type-C products
UHD TVs

Deliverables

Encrypted RTL source code IP core
Functional and structural coverage reports
Comprehensive integration guide
Technical support and maintenance updates

Technical Specifications

Request Info