MIPI D-PHY CSI-2 TX (Transmitter) in TowerJazz 65BSB

Overview

Key Features

• Supports MIPI Alliance Specification for D-PHY Version 2.5
• Consists of 1 Clock lane and 2 Data lanes in D-PHY mode
• 80 Mbps to 1.2 Gbps data rate per lane in high-speed D-PHY mode
• Supports LVDS compatible with TIA/EIA-644 standard
• Consists of 3 channels in LVDS mode
• 600 Mbit/s/channel in LVDS mode
• Supports both 8-bit serial data and 10-bit serial data for LVDS
• LVDS current configurable
• Embedded, high performance, and highly programmable PLL
• PLL has 2 independent dividers at the output of the VCO: one divider for core circuits and one for MIPI. The 2 dividers have independent settings of division factor.
• Supports both low-power mode and high-speed mode with integrated SERDES
• 10 Mbps data rate in D-PHY low-power mode
• Low power dissipation
• Supports operation with reduced amount of data lanes. Unused data lanes can be put in power-down mode in which all current paths shall be cut and no current shall flow.
• Testability support

Benefits

• Support for both MIPI D-PHY and LVDS

Block Diagram

Applications

• Mobile
• Cameras/Sensors
• IoT
• VR/AR/MR
• Consumer electronics
• Automotive

Deliverables

• Specifications
• GDSII
• LVS netlist
• LEF file
• IBIS Model
• Verilog Model
• Timing Model
• Integration Guidelines
• RTL
• Documentation
• One year support

Technical Specifications