MIPI CSI-2 TX Controller

Overview

CSI-2 transmitter controller for application processor

The Transmitter (TX) Controller IP for MIPI^® Camera Serial Interface 2 (CSI-2^sm) is responsible for handling image sensor data in multiple RGB, YUV, and RAW formats, and user-defined data formats, while converting these into CSI-2-compliant packets for transmission over a D-PHY^sm interface via the PPI interface.

The TX Controller IP for CSI-2 can handle up to four independent pixel streams and can perform Virtual Channel and Data Type interleaving before transmission four PPI data lanes.

Key Features

Standards Compliance. CSI-2 v2.1, with 8-bit PPI data width and links with 1, 2, or 4 data lanes
Provides up to 4 Independent Stream Output Interfaces, allowing a highly configurable range of options, including multiple pixel modes, various buffering modes, packed data mode, Data Type selection, and Virtual Channel or Data Type interleaving

Block Diagram

Applications

Automotive,
Communications,
Consumer Electronics,
Data Processing,
Industrial and Medical,
Military/Civil Aerospace,
Others

Deliverables

Unencrypted, synthesizable Verilog HDL
Cadence Genus™ Synthesis Solution scripts
Documentation—Integration and User Guide, Release Notes
Demonstration testbench with integrated Cadence Verification IP (VIP)
Software Driver

Technical Specifications

Maturity

Silicon Proven

Request Info