Innosilicon MIPI DSI Transmitter implements the DSI protocol as well as MIPI C-PHY protocol. The DSI link protocol specification is a part of group of communication protocols defined by MIPI® Alliance standards intended for mobile system chip to chip communications. The MIPI DSI specification is specifically targeted for the display communication in image application processors.
Innosilicon MIPI DSI Transmitter operates as a transmitter of a DSI link, which consists of a C-PHY and a DSI Controller.
? The Innosilicon C-PHY is used for the data transmission from a DSI compliant display module. In C-PHY, the link includes a High-Speed signaling for fast-data traffic and a low-power signaling mode for control purposes. Error information is generated for application layer to do further operation.
? Innosilicon MIPI DSI Controller works as a protocol layer between application layer and physical layer, which mainly aims to pack and distribute the pixels to the physical layers. Innosilicon DSI Controller implements all three layers defined by MIPI DSI specification, including Pixel/Byte Packing, Low Level Protocol, and Lane Management.
MIPI C-PHY DSI TX IP
Overview
Key Features
- Compliant with MIPI® Alliance Specification for Display Serial Interface (DSI) V1.2
- Compliant with MIPI® Alliance Standard for Display Bus Interface (DBI) V2.0
- Compliant with MIPI® Alliance Standard for Display Pixel Interface (DPI) V2.0
- Compliant with MIPI® Alliance Specification for C-PHY V1.1
- Compliant with MIPI® Alliance Specification for Display Command Set (DCS) V1.3
- Compliant with AMBA V3.0 APB Specification
- Supports data type: RGB/YCbCr (based on actual application scenarios)
- Data transfer rate ranges from 450Msps to 2.5Gsps per trio (C-PHY)
- Supports DPI for video mode interface
- Supports DBI for command mode interface
- Type A Clocked E mode for DBI interfaces
- Supports HS, LP and ULPS modes
- Bidirectional communication and escape mode support through trio 0
- Automatic termination control for HS and LP modes
- On die low jitter PLL integrated
Deliverables
- Databook and physical implementation guides Netlist (Spice format for LVS)
- Library Exchange Format (LEF)
- Encrypted Verilog Models
- GDSII to Foundry IP Merge
- Module integration guidelines
- Silicon validation report (when available)
- Evaluation board (when available)
Technical Specifications
Foundry, Node
SMIC 40nm
SMIC
In Production:
40nm
LL
Silicon Proven: 40nm LL
Silicon Proven: 40nm LL
Related IPs
- MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI C-PHY v1.0 D-PHY v1.2 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3P)
- MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm, 12nm, N5)
- MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm) for Automotive
- MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)