MIPI DSI TX Controller

Overview

DSI transmitter controller for application

Compliant with the MIPI^® Alliance Specification for Display Serial Interface (DSI^sm), the TX Controller IP for DSI provides the interface from a host device graphics controller to one or more display modules and includes an arbitration layer for arbitrating among the various data and command streams, a DSI protocol layer for protocol functions, and a lane management layer (LML) to distribute the DSI data stream across the active D-PHY^sm lane modules.

Key Features

Compliant with MIPI DSI v1.3.1, supporting Command Mode, Video Mode, and bi-directional low-power data transmission (LPDT)
Range of Display Formats Supported. Cadence Serial Display Interface (SDI), MIPI Display Pixel Interface (DPIsm), and Display Compression (DSC) input interface option
Programmable Test Video Generator with integration debug and test

Benefits

Flexible Interface Options: Including support for DPI, SDI, and DSC
Flexible Command Mode Support: APB interface or SDI
Automotive Version Available: With safety manual and FMEDA

Block Diagram

Deliverables

Unencrypted, synthesizable Verilog HDL
Cadence Genus™ Synthesis Solution scripts
Documentation—Integration and User Guide, Release Notes
Demonstration testbench, using System Verilog and Cadence Verification IP (VIP)
Software driver

Technical Specifications

Maturity

Silicon Proven

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