MIPI C-PHY/D-PHY Combo Universal IP in UMC 40LP

Overview

The MXL-CPHY-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY can be configured as a MIPI Master or MIPI Slave supporting camera interface CSI-2 v1.2 and display interface DSI v1.3 applications in the D-PHY mode. It also supports camera interface CSI-2 v1.3 and display interface DSI-C v1.0 applications in the C-PHY mode. The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.

Key Features

Dual mode PHY can support C-PHY and D-PHY
Supports MIPI Specification for D-PHY Version 1.2
Supports MIPI Specification for C-PHY Version 1.0
Four Lane in D-PHY mode
Three Lane in C-PHY mode
Supports both high speed and low-power modes
D-PHY: 80 Mbps to 2.5Gbps data rate per lane in high speed mode
C-PHY: up to 2.5G symbol/sec
10 Mbps data rate in low-power mode
Low power dissipation
Loopback testability support
Optional resistance termination calibrator
Deskew calibration support in D-PHY

Benefits

Compatible with both C-PHY 1.0 and D-PHY 1.2 specifications for added flexibility

Block Diagram

Applications

Mobile
Displays
Cameras/Sensors
IoT
VR/AR/MR
Consumer electronics
Automotive

Deliverables

Specifications
GDSII
LVS netlist
LEF file
IBIS Model
Verilog Model
Timing Model
Integration Guidelines
RTL
Documentation
One year support

Technical Specifications

Foundry, Node

UMC, 40LP

Maturity

Silicon Proven

Availability

Now

UMC

Silicon Proven: 40nm LP

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