The LVDS library provides an LVDS driver, receiver, and temperature stable voltage reference capable of supporting 16 drivers operating at data rates up to 2.4 Gbps. Also included is a full complement of power, spacer, and adapter cells to assemble a complete pad ring by abutment. An included rail splitter allows isolated LVDS domains to be placed in the same pad ring with other power domains while maintaining continuous VDD/VSS in the pad ring for robust ESD protection.
This 22nm library is available in a staggered CUP wire bond implementation with a flip chip option.
LVDS IO Pad Set
Overview
Key Features
- LVDS Receiver Features:
- ? Operates up to 1.2 GHz (2.4 Gbps)
- ? Input receive sensitivity of 75mV peak differential (without hysteresis)
- ? Duty Cycle Distortion (DCD) – 50 ps typical
- ? Common mode range from 0V to 1.8V (limited by power supply)
- LVDS Driver Features:
- ? Operates up to 1.0 GHz (2.0 Gbps) with external 1 pF load
- ? Common mode output range 1.1V ±100mV
- ? Supports single termination (far end) only – 100? differential
Deliverables
- a. Physical abstract in LEF format (.lef)
- b. Timing models in Synopsys Liberty formats (.lib and .db)
- c. Calibre compatible LVS netlist in CDL format (.cdl)
- d. GDSII stream (.gds)
- e. Behavioral Verilog (.v)
- f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- g. Databook (.pdf)
- h. Library User Guide - ESD Guidelines (.pdf)
Technical Specifications
Foundry, Node
GLOBALFOUNDRIES, 22nm
Maturity
Silicon Proven
Availability
Available Now
GLOBALFOUNDRIES
Silicon Proven:
22nm
FDX
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