LVDS I/O Pad Set

Overview

The LVDS library provides an LVDS driver, receiver, and
temperature stable voltage reference capable of supporting 16 drivers
operating at data rates up to 2.4 Gbps. The pad set includes a full
complement of power, spacer, and adapter cells to assemble a
complete pad ring by abutment. An included rail splitter allows
isolated LVDS domains to be placed in the same pad ring with other
power domains while maintaining continuous VDD/VSS in the pad
ring for robust ESD protection.
? 1.2 GHz LVDS Driver
? 1.2 GHz LVDS Receiver with CML output
? 2.0 GHz LVDS Receiver
? LVDS Voltage Reference
Ported from our TSMC 16 silicon proven design.

Key Features

LVDS Receiver Features:
? Operates up to 2.0 GHz (4.0 Gbps)
? Input receive sensitivity of 75mV peak differential (without hysteresis)
? Duty Cycle Distortion (DCD) – 50 ps typical
? Common mode range from 0V to 2.4V (limited by power supply)
? Powered by 1.8V I/O and 0.8V core supplies
LVDS Receiver Features:
? DOUT operates up to 1.2 GHz (2.4 Gbps)
? CML Out operates up to 800 MHz (1.6 Gbps)
? Input receive sensitivity of 100mV with hysteresis and 75mV without hysteresis (peak differential)
? Duty Cycle Distortion (DCD) – 50 ps typical
? Common mode range from 0V to 2.4V (limited by power supply)
? Powered by 1.8V I/O and 0.8V core supplies

Deliverables

a. Physical abstract in LEF format (.lef)
b. Timing models in Synopsys Liberty formats (.lib and .db)
c. Calibre compatible LVS netlist in CDL format (.cdl)
d. GDSII stream (.gds)
e. Behavioral Verilog (.v)
f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
g. Databook (.pdf)
h. Library User Guide - ESD Guidelines (.pdf)

Technical Specifications

Foundry, Node

TSMC 12nm

Maturity

Silicon Proven

Availability

Available Now

TSMC

Pre-Silicon: 12nm
Silicon Proven: 12nm

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LVDS I/O Pad Set

Overview

Key Features

Deliverables

Technical Specifications

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