LVDS I/O Pad Set

Overview

The LVDS library provides an LVDS driver, receiver, and temperature stable voltage reference capable of supporting 16 drivers operating at data rates up to 4.0 Gbps. The pad set includes a full complement of power, spacer, and adapter cells to assemble a complete pad ring by abutment. An included rail splitter allows isolated LVDS domains to be placed in the same pad ring with other power domains while maintaining continuous VDD/VSS in the pad ring for robust ESD protection.

? 2.0 GHz LVDS Driver
? 2.0 GHz LVDS Receiver
? LVDS Voltage Reference

This 7nm library is available in a staggered flip chip implementation.

LVDS Specification Compliant:
• TIA/EIA-644-A - Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits
• IEEE Std 1596.3-1996

ESD Protection:
? JEDEC compliant
o 2KV ESD Human Body Model (HBM)
o 500 V ESD Charge Device Model (CDM)

Latch-up Immunity:
? JEDEC compliant
o Tested to I-Test criteria of ± 100mA @ 125°C

Deliverables

  • a. Physical abstract in LEF format (.lef)
  • b. Timing models in Synopsys Liberty formats (.lib and .db)
  • c. Calibre compatible LVS netlist in CDL format (.cdl)
  • d. GDSII stream (.gds)
  • e. Behavioral Verilog (.v)
  • f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
  • g. Databook (.pdf)
  • h. Library User Guide - ESD Guidelines (.pdf)

Technical Specifications

Foundry, Node
TSMC 7nm
Maturity
Silicon Proven
Availability
Available Now
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Semiconductor IP