High performance, low power and area efficient memory interface solutions conforming to LPDDR5/5X (JESD209-5C) JEDEC standard
LPDDR5/5X PHY & Controller
Overview
Key Features
- One stop PHY & Controller solution with an average random efficiency of more than 85%
- Supports up to 6400 MT/s rates with upgradable option to 8533 MT/s
- DFI 5.0 compliant interface to the memory controller
- I/Os include receiver decision feedback equalization (DFE) and transmitter feed forward equalization (FFE)
- Flexible PHY with programmable intelligent interface training sequences
- Supports x8, x16 and x32 SDRAMs
- Supports up to 32Gb addressing
- Supports up to BG, 8B and 16B bank modes
- Add-on features/engines for MPFE, RAS and Debug available upon request