High-performance 32-bit Superscalar Processor

Overview

Key Features

• Instruction set: T-Head ISA (32-bit/16-bit variable-length instruction set);
• Pipeline: 10-stage;
• Microarchitecture: Dual-issue, out-of-order;
• General register: 32 32-bit GPRs; 16 128-bit VGPRs;
• Cache: 2-stage cache; I-cache: 16 KB/32 KB/64 KB (size options); D-cache: 16 KB/32 KB/64 KB (size options);
• Bus interface: Dual bus (system bus + peripheral bus);
• Memory protection: On-chip memory management unit supports hardware backfilling;
• Floating point engine: Supports single and double precision floating point operations;
• Vector calculation engine: 128-bit operation width, supporting 8-bit/16-bit/32-bit shaping and fixed-point parallel computing;
• -bit/32-bit shaping and fixed-point parallel computing
• Secure execution technology: Hardware assisted build of a secure execution environment;
• Performance monitoring: Supports a hardware performance monitoring unit;
• High-Performance memory access: Supports out-of-order memory access, data prefetch and write combining to further expand memory bandwidth;
• Hybrid branch processing: Hybrid branch processing technology including branch direction, branch target address and function return address prediction to improve fetching efficiency;
• Vector calculation engine: Improves computing parallelism, and speeds up typical scenarios such as DSP and multimedia;
• Secure execution technology: Resists any hardware and software attacks, and increases system security.

Block Diagram

Applications

• Speech Recognition;
• Intelligent Vision;
• Smart Home Appliances.

Technical Specifications